Highly integrated semiconductor circuits are increasingly important, particularly in producing battery operated devices such as cell phones, portable computers such as laptops, notebook computers and PDAs, wireless email terminals, MP3 audio and video players, portable wireless web browsers and the like, and these sophisticated integrated circuits increasingly include on-board data storage.
As is known in the art, such data storage may take the form of dynamic memory cells in which arrays of capacitive storage memory cells are provided. In the conventional dynamic memory devices of most current integrated circuits, a one transistor-one capacitor (1T1C) memory cell is frequently employed, each memory cell having an access transistor and a capacitor. Data stored in such memory cells is actually a charge stored on the small capacitor, and the data is typically accessed by outputting the stored charge to a bit line, which is then coupled to a sense amplifier. The data is output when the access transistor is activated, typically by a word line coupled to the gate or control terminal of the transistor. Sense amplifiers coupled to the bit lines are typically differential sense amplifiers. The input and output lines coupled from the memory cells to the memory array sense amplifier are typically referred to as bit lines or column lines. The sense amplifier operates by receiving a small differential voltage, typically on the order of 200 millivolts for current process technology DRAMs, on one of the bit lines, while the other bit line remains at, or is coupled to, a reference voltage. The small differential voltage between the pairs of bit lines is sensed by the sense amplifier and then amplified to a larger voltage that additional circuitry can receive, for example VDD or VSS.
To enable large arrays of memory cells to be used in implementing a typical memory device, pairs of global bit lines coupled to a latching sense amplifier are often routed though the memory array, while pairs of local bit lines for transmitting and receiving read and write data to and from the global bit lines are formed in columns in sub-arrays, the local bit lines are usually arranged as columns coupled to rows of memory cells. The global bit lines may also be coupled to an input/output circuit that transfers the memory array data to and from other circuits. Because the voltages developed at the bit lines by the conventional dynamic memory cell are quite small, a plurality of sense amplifiers, and local and global bit lines, are required to correctly deliver the data out of the memory cells. The memory cells output data by a charge sharing mechanism, which slowly transfers charge from the storage capacitor onto the selected bit line. The memory cell must be “written back” to restore the small stored charge at the end of each read cycle, because the storage capacitor discharges onto the bit line, the read is a destructive read out.
Dynamic memory cells may be used in stand alone, or commodity, memory devices such as DRAM integrated circuits. These ICs are usually supplied in the form of cards populated with several commodity DRAM integrated circuits to make a complete array of memory, for example so called SIMM or DIMM cards. These cards are then provided as a finished memory product for a desktop or laptop computer. Increasingly embedded dynamic memory is becoming important in the production of advanced integrated circuits. These embedded memory modules may be a portion of an integrated circuit that provides an entire system in one IC, so-called system on a chip (SOC) or system on integrated circuit (SOIC) devices. These SOC devices may provide, for example, all of the circuitry needed to implement a cell phone, or a personal data assistant (PDA), digital VCR, digital camcorder, digital camera, MP3 player, or the like in a single integrated circuit. The embedded memory arrays used in such devices must be very space efficient, must be very power efficient, reliable and must be compatible with semiconductor processes that form logic circuitry and other types of circuitry on board the same integrated device. Typically the embedded dynamic memory in such integrated circuits is referred to as e-DRAM.
The charge sharing mechanism used by conventional DRAM cell accesses causes reads of the memory cell to be destructive, and requires a write back cycle after a read, lengthening the time required for each read cycle. The cells require large capacitors and frequent refresh cycles, which reduce memory density and slow access times. A need thus exists for improved DRAM memory devices.